1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device including a duty-cycle correction circuit.
2. Description of Related Art
In a semiconductor device that performs operations in synchronization with a clock signal, such as a synchronous DRAM (Dynamic Random Access Memory), an internal clock signal that is phase-controlled may be required. The phase-controlled internal clock signal is mainly generated by a DLL (Delay Locked Loop) circuit. In a general DLL circuit, the phase control is performed by adjusting a rising edge timing of the internal clock signal.
Meanwhile, in a DDR (Double Data Rate) DRAM, input and output of data are performed in synchronization with both a rising edge and a falling edge of the internal clock signal, and therefore it is required to accurately control a falling edge timing as well as a rising edge timing. The falling edge timing of the internal clock signal is generally adjusted by a circuit referred to as “duty-cycle correction circuit”.
A general duty-cycle correction circuit includes two capacitors, of which one capacitor is discharged when an internal clock signal is at a high level and the other capacitor is discharged when the internal clock signal is at a low level. When the duty cycle of the internal clock signal is 50%, the two capacitors are equally discharged, and no potential difference is generated between the two capacitors. This state means that a period from the rising edge to the falling edge (or a period from the falling edge to the rising edge) of the internal clock signal is exactly ½ of a clock cycle. On the other hand, when the duty cycle of the internal clock signal is less than or larger than 50%, the discharge amounts of the two capacitors are not equal to each other, and accordingly a potential difference is generated between the two capacitors. This state means that the period from the rising edge to the falling edge (or the period from the falling edge to the rising edge) of the internal clock signal is shifted from ½ of a clock cycle. In this case, control is performed to make the duty cycle close to 50% by advancing or delaying the falling edge timing.
However, the general duty-cycle correction circuit mentioned above has some problems explained as follows.
The first problem is that two capacitors with a relatively large capacitance are required. Because a capacitor with a large capacitance occupies a large area on a semiconductor chip, the chip area is increased. The second problem is that an analog amplifier circuit is required to detect a potential difference generated between the two capacitors. While a highly-accurate analog amplifier circuit is required to detect a minute potential difference, it is difficult to obtain the high accuracy due to various factors such as a fluctuation of a threshold value generated between a plurality of transistors. The third problem is that a discharge operation needs to be performed across a plurality of clock cycles to amplify a potential difference generated between two capacitors, so that it takes time to detect the duty cycle. The fourth problem is that potentials of capacitors need to be maintained correctly during a discharge operation is performed across clock cycles. This means that the duty-cycle correction circuit is likely to be affected by noise, which makes it difficult to perform a stable duty-cycle determination operation. The fifth problem is that, when the duty cycle of the internal clock signal is near 50%, there is little potential difference between two capacitors, which is likely to cause a malfunction of the device. This problem becomes more conspicuous when the frequency of the internal clock signal is high, because the higher the frequency of the internal clock signal is the shorter a discharge period becomes.
As a duty-cycle correction circuit that solves these problems, the present invertor have proposed a new type of duty-cycle correction circuit (see Japanese Patent Application Laid-open No. 2011-199617). The duty-cycle correction circuit disclosed in Japanese Patent Application Laid-open No. 2011-199617 performs an operation of setting a count value to ½ by a calculation when a delay amount of a delay line is one clock cycle and an operation of specifying a falling edge timing of an internal clock signal from a delay amount obtained by the value. The duty-cycle correction circuit disclosed in Japanese Patent Application Laid-open No. 2011-199617 is an excellent circuit that solves the five problems mentioned above.
However, there may be a case where a plurality of delay elements that constitute a delay line do not necessarily have the same delay amount. This is because some resistive elements and capacitive elements for adjustment are connected to the delay line for a fine adjustment of the delay amount. In this case, even if the count value is set to ½ when the delay amount of the delay line is one clock cycle, it is not always the case that the delay amount obtained by the value is correctly ½ of a clock cycle. This problem occurs not only in the duty-cycle correction circuit used in a DLL circuit, but also any type of circuit that requires accurate control of the duty cycle of the clock signal.